Semiconductor device allowing electrical writing and erasing of information and method of manufacturing the same

ABSTRACT

In a semiconductor device and a method of manufacturing the same, two floating gate electrodes are independently controlled with one control gate electrode. In the semiconductor device, the first floating gate electrode is formed on a channel region with a first gate insulating film therebetween, and the control gate electrode is formed on the first floating gate electrode with a first interlayer insulating film therebetween. The second floating gate electrode exists on the control gate electrode and has a portion extended above a semiconductor substrate and overlapping with a second impurity diffusion layer. A first impurity diffusion layer overlaps with an end of the first floating gate electrode. Thereby, writing, erasing and reading are effected on the two, i.e., first and second floating gate electrodes with one control gate electrode while maintaining the substantially same memory cell area as the prior art.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and amethod of manufacturing the same, and in particular, to a semiconductordevice allowing electrical writing and erasing of information as well asa method of manufacturing the same.

[0003] 2. Description of the Background Art

[0004] As a kind of semiconductor memory device, there has been known anonvolatile semiconductor memory device. As a kind of nonvolatilesemiconductor memory device, there has been known an EEPROM(Electrically Erasable and Programmable Read Only Memory) in which datacan be freely programmed and which allows electrical writing and erasingof information. Although the EEPROM has an advantage that both writingand erasing can be executed electrically, it disadvantageously requirestwo transistors for each memory cell, and therefore integration to ahigher degree is difficult. For this reason, there has been proposed aflash EEPROM including memory cells, each of which is formed of onetransistor, and allowing electrical entire chip erasing of writtenelectric information charges. This is disclosed, for example, in U.S.Pat. No. 4,868,619. This flash memory is suitable for high integrationbecause each memory cell is formed of one transistor as described above.

[0005]FIG. 25 is an equivalent circuit diagram fragmentarily showing amemory cell array structure of a conventional flash memory. Referring toFIG. 25, M00-M35 indicate memory transistors functioning as memoryelements. A drain, a gate and a source in each memory transistor areconnected to a corresponding bit line (BL0-BL3), a corresponding wordline (WL0-WL5) and a source line (SL0), respectively.

[0006]FIG. 26 is a plan showing an actual pattern structure of thememory cell array shown in FIG. 25. Referring to FIG. 26, lines BL0-BL3,WL0-WL5 and SL0 correspond to the bit lines, word lines and source linedenoted by the same reference characters in FIG. 25. Element isolatingregions 1 are formed at predetermined regions with a predetermined spacebetween each other. Floating gate electrodes 3 are formed atpredetermined regions under word lines (WL0-WL5), and control gateelectrodes 5 connected to the word lines are formed on floating gateelectrodes 3. Metal interconnections 8 made of, e.g., aluminuminterconnections and forming bit lines (BL0-BL3) extend perpendicularlyto word lines (WL0-WL5).

[0007] FIGS. 27 to 32 are cross sections taken along line 100-100 inFIG. 26 and showing the structure during manufacturing in accordancewith the order of process steps. FIGS. 33 to 37 are cross sections takenalong line 200-200 in FIG. 26 and showing the structure duringmanufacturing in accordance with the order of process steps. Referringto FIGS. 27 to 37, the manufacturing process of the conventional flashmemory will be described below.

[0008] First, as shown in FIG. 27, element isolating regions 1 areformed on a surface of a semiconductor substrate 101 by the LOCOS (LOCalOxidation of Silicon) method of the like. Then, as shown in FIG. 28,first gate oxide films 2 a are formed, e.g., by the thermal oxidationmethod on portions of the surface of semiconductor substrate at whichelement isolating regions 1 do not exist. A polycrystalline silicon film(not shown) is deposited by the CVD (Chemical Vapor Deposition) method,and subsequently is patterned along an extending direction of the wordline by the photolithography and dry etching technique. Thereby, firstgate electrodes 3 a are formed.

[0009] Then, as shown in FIG. 33, an interlayer insulating layer 4 a isformed on first gate electrodes 3 a by the thermal oxidation method orCVD method. A second gate electrode 5 a formed of a polycrystallinesilicon film or a polycide film (i.e., multilayer film formed of apolycrystalline silicon film and a metal silicide film of a high meltingpoint) is formed on interlayer insulating layer 4 a by the CVD method.The photolithography and dry etching technique are executed to patternsecond gate electrode 5 a, interlayer insulating layer 4 a, first gateelectrode 3 a and first gate oxide film 2 a to extend themperpendicularly to the extending direction of the word line. Thereby,first gate oxide films 2, floating gate electrodes 3, interlayerinsulating layers 4 and control gate electrodes 5 are formed as shown inFIGS. 29 and 34. Thereafter, impurity is ion-implanted intosemiconductor substrate 101 to form drain regions 13 and source regions14 using the control gate electrodes 5 as a mask.

[0010] As shown in FIGS. 30 and 35, an interlayer insulating layer 6 isformed, e.g., by the CVD method, and contact holes 7 are formed by thephotolithography and dry etching technique.

[0011] As shown in FIGS. 31 and 36, a metal interconnection layer (notshown) made of, e.g., aluminum alloy is formed on the whole surface bythe sputtering method or the like, and subsequently is patterned by thephotolithography and dry etching technique. Thereby, metalinterconnection layers 8 forming the bit lines and source line areformed.

[0012] As shown in FIGS. 32 to 37, a surface protective film 9 is formedby the CVD method. Surface protective film 9 covers portions other thanbonding pad connections (not shown). In this manner, the conventionalflash memory is completed.

[0013] Operation of the conventional flash memory will be describedbelow. The flash memories of 1 to 8 megabits which are now available areoperated by the CHE injection writing, i.e., writing by injection ofchannel hot electrons and the tunnel erasing, i.e., tunnel removalthereof from a source. As another method of writing and erasing in theflash memory, the tunnel writing and tunnel erasing may be employed, bywhich both writing and erasing are carried out with a tunnel current.

[0014]FIG. 38 shows a concept of variation of memory transistorcharacteristics caused by writing and erasing. FIG. 39 shows a conceptof writing of a flash memory by the CHE injection. FIG. 40 shows aconcept of erasing of the flash memory by the tunnel erasing.

[0015] For performing writing by the CHE injection, semiconductorsubstrate 101 and source region 14 of the memory transistor, on whichwriting is effected, are grounded as shown in FIGS. 38 and 39. A voltageVd from 5V to 8V is applied to drain region 13 via the bit line. Avoltage Vg from 10V to 13V is applied to control gate electrode 5 viathe word line. Thereby, hot electrons generated by high electric chargesnear the drain are injected into floating gate electrode 3. Bymaintaining the electrons in floating gate electrode 3, the thresholdvoltage of memory transistor is shifted, so that the writing iscompleted.

[0016] The writing can be performed in either a timing mode similar tothat of the conventional EPROM or a command mode in which a chipinternally and automatically performs 100 the writing in accordance witha command and a data applied thereto. In either mode, a write depth atthe written position is generally verified, and, if shallow, additionalwriting is effected. More specifically, as shown in FIG. 41, a writepulse is applied at step S1, and write verification is performed atsubsequent step S2. If the result of write verification represents theshallow write, the process returns to step S1 for additional writing. Ifthe result of write verification represents the sufficient writing, thewriting is completed as indicated at step S3.

[0017] The tunnel erasing will be described below with reference toFIGS. 38 and 40. For the tunnel erasing, drain region 13 is set to afloating state, and control gate electrode 5 and semiconductor substrate10 are grounded. A high voltage Vs, e.g., from 8V to 12V is applied tosource region 14. In this case, the potential of floating gate electrode3 depends on the potential set by electrons in floating gate electrode 3as well as capacitance coupling between the floating gate and controlgate, between floating gate and source region and between floating gateand substrate.

[0018] Since an area of overlapped portions of floating gate electrode 3and source region 14 is small relatively to a whole area of the channelregion, a capacitance between the floating gate electrode and sourceregion is small relatively to a capacitance between the floating gateand control gate and a capacitance between the floating gate andsubstrate. Therefore, the potential of floating gate electrode 3 isrelatively close to the potential (ground potential) of control gateelectrode 5 and semiconductor substrate 101. In this case, if electronsare accumulated in the floating gate electrode 3, the potential offloating gate electrode 3 further decreases. Therefore, a strongelectric field is produced across floating gate electrode 3 and sourceregion 14, so that the electrons in floating gate electrode 3 areremoved into source region 14 by this strong electric field. In thismanner, erasing of the memory transistor is performed.

[0019] In the flash memory, entire chip erasing is executed or it iserased a block at a time. Therefore, if the bits are maintained atdifferent states, i.e., data written state and data unwritten statebefore the erasing, the bits having a low threshold voltage will beover-erased to attain the depletion state, resulting in increase of aproportion of defective. Generally, variation of the threshold voltageis suppressed by entire bit writing before the erasing, as shown in FIG.42. More specifically, after the entire bit writing, an erase pulse isapplied at step S5, and it is checked at step S6 whether the erasing isactually executed. If the erasing is insufficient, the process returnsto step S5 to apply the erase pulse again. If the erasing is sufficient,the erasing process is completed as indicated at step S7.

[0020] The tunnel writing will now be described below. In this case, thewriting is executed by the tunnel current from semiconductor substrate101 through first gate insulating film 2. For example, voltage Vg ofabout 10V is applied to control gate electrode 5, and voltage Vs ofabout −10V is applied to semiconductor substrate 101.

[0021] As compared with the tunnel erasing from source region 14, thetunnel writing causes a large potential difference between control gateelectrode 5 and semiconductor substrate 101. In this tunnel writing,however, a capacitance between the control gate and floating gate issubstantially equal to a capacitance between the floating gate andsubstratus, so that floating gate electrode 3 has a potential nearlyintermediate the potentials of semiconductor substrate 101 and controlgate electrode 5, and thus an electric field across the floating gateand substrate is nearly equal to that in the source erasing.

[0022] Instead of applying the write voltage to semiconductor substrate101, the voltage applied to control gate electrode 5 may be raised toabout 20V, which also enables writing. In a device of a design rulelevel not exceeding lam, however, an impurity diffusion layer has a lowjunction breakdown voltage not exceeding about 10V, so that it isdifficult to use the high voltage of about 20V in such a minute device.

[0023] Instead of the aforementioned method of removing electrons fromsource region 14, erasing may be executed by such a method thatelectrons are removed from floating gate electrode 3 to semiconductorsubstrate 101 through first gate insulating film 2 in a manner oppositeto the tunnel writing. In this case, erasing is executed by applying anegative voltage of about −10V to control gate electrode 5 and applyinga positive voltage of about 10V to semiconductor substrate 101.

[0024] In the conventional flash memory, since each memory element isformed of one transistor as described above, the cell structure is moresuitable for miniaturization than those of other semiconductor memorydevices. However, the degree of integration of the flash memory dependson the process limit or work limit of the apparatus manufacturing thesemiconductor device. Therefore, it has been very difficult tominiaturize the flash memory to an extent exceeding the process limit ofthe semiconductor device manufacturing apparatus.

SUMMARY OF THE INVENTION

[0025] An object of the invention is to provide a semiconductor devicewhich can be integrated to a higher extent with a miniaturizingtechnique of the same level as the prior art.

[0026] Another object of the invention is to provide a method allowingeasy manufacturing of a semiconductor device, of which degree ofintegration is higher than that in the prior art, with a miniaturizingtechnique of the same level as the prior art.

[0027] A semiconductor device of one aspect of the invention includes asemiconductor substrate, first and second impurity regions, a firstfloating gate electrode, a control gate electrode and a second floatinggate electrode. The semiconductor substrate has a main surface, and isof a first conductivity type. The first and second impurity regions areformed on the main surface of the semiconductor substrate with apredetermined space defining a channel region therebetween, and are of asecond conductivity type. The first floating gate electrode is formed onthe channel region with a first gate insulating film therebetween andhas an end overlapping with the first impurity region. The control gateelectrode is formed on an upper surface of the first floating gateelectrode with a first interlayer insulating film therebetween. Thesecond floating gate electrode is formed on an upper surface and a sidesurface of the control gate electrode with a second interlayerinsulating film therebetween, and is formed on the channel region with asecond gate insulating film therebetween to have an end overlapping withthe second impurity region. Preferably, the second floating gateelectrode may be extended over the first impurity region with the secondgate insulating film therebetween. Preferably, the second floating gateelectrode may have the other end located above a region at which thecontrol gate electrode is formed.

[0028] According to the semiconductor device of the above aspect, thefirst floating gate electrode has the end overlapping with the firstimpurity region and the second floating gate electrode formed on theupper surface of the control gate electrode on the first floating gateelectrode has the end overlapping pith the second impurity region.Therefore, the semiconductor device can independently effect writing,erasing and reading of data on the two, i.e., first and second floatinggate electrodes with one control gate electrode. Thereby, the memorycapacitance can be doubled with the substantially same memory size asthat in the prior art.

[0029] According to another aspect of the invention, a semiconductordevice allowing electrical writing and erasing of information includes asemiconductor substrate, first and second impurity regions, a firstfloating gate electrode, a second floating gate electrode and a controlgate electrode. The second floating gate electrode is formed on an uppersurface and a side surface of the first floating gate electrode with afirst interlayer insulating film therebetween, and is formed on achannel region with a second gate insulating film therebetween to havean end overlapping with the second impurity region. The control gateelectrode is formed on the upper surface of the first floating gateelectrode with the first interlayer insulating film therebetween, and isformed on a side surface and an upper surface of the second floatinggate electrode with a second interlayer insulating film therebetween.

[0030] According to the semiconductor device of the above aspect, thefirst floating gate electrode has the end overlapping with the firstimpurity region, the second floating gate electrode formed on the firstfloating gate electrode has the end overlapping with the second impurityregion, and the first and second floating gate electrodes are coveredwith the control gate electrode. Therefore, semiconductor device canindependently effect writing, erasing and reading of data on the two,i.e., first and second floating gate electrodes with one control gateelectrode. Thereby, the memory capacitance can be doubled with thesubstantially same memory size as that in the prior art.

[0031] According to still another aspect of the invention, asemiconductor device allowing electrical writing and erasing ofinformation includes a semiconductor substrate, first and secondimpurity regions, a first floating gate electrode, a second floatinggate electrode and a control gate electrode. The second floating gateelectrode is formed on a channel region with a first gate insulatingfilm therebetween to form a predetermined space with respect to thefirst floating gate electrode and has an end overlapping with the secondimpurity region. The control gate electrode is formed on upper surfacesand side surfaces of the first and second floating gate electrodes witha first interlayer insulating film therebetween and is formed on thechannel region with a first gate insulating film therebetween.Preferably, a third impurity region may be formed at a region of thechannel region located between the first floating gate electrode and thesecond floating gate electrode.

[0032] According to the semiconductor device of the above aspect, thefirst and second floating gate electrodes are formed on the first gateinsulating film with a predetermined space between each other and havethe ends overlapping with the first and second impurity regions,respectively. The control gate electrode is formed on not only the uppersurfaces but also the side surfaces of the first and second floatinggate electrodes with the first interlayer insulating film therebetween.Therefore, a capacitance is increased by an amount corresponding to theportion of the control gate electrode formed on the side surface of thesecond floating gate electrode. Thereby, the capacitance coupling ratioincreases, so that the potential of the floating gate increases duringwriting and erasing. Consequently, writing and easing can be executedeasily. Also this semiconductor device independently effects writing,erasing and reading of data on the two, i.e., first and second floatinggate electrodes with one control gate electrode. Thereby, the degree ofintegration can increase to some extent as compared with the prior art.A third impurity region may be formed at a region between the firstfloating gate electrode and the second floating gate electrode, whichprevents formation of a parasitic transistor at the above region.

[0033] According to a method of manufacturing a semiconductor device ofan aspect of the invention, a first gate insulating film is formed on amain surface of a semiconductor substrate of a first conductivity type.A first floating gate electrode is formed on the first gate insulatingfilm. A control gate electrode is formed on the first floating gateelectrode with a first interlayer insulating film therebetween. Impurityis introduced into the semiconductor substrate using the first floatinggate electrode as a mask to form a first impurity region of a secondconductivity type having a region overlapping with an end of the firstfloating gate electrode. A second interlayer insulating film is formedon an upper surface and a side surface of the control gate electrode anda side surface of the first floating gate electrode. A second gateinsulating film is formed on the main surface of the semiconductorsubstrate. A second floating gate electrode is formed on the secondinterlayer insulating film and the second gate insulating film to have aportion located on the control gate electrode and at least an endextended to a position on the semiconductor substrate near the other endof the first floating gate electrode. Impurity is introduced into thesemiconductor substrate using the second floating gate electrode as amask to form a second impurity region of the second conductivity typehaving a region overlapping with an end of the second floating gateelectrode.

[0034] Thereby, the method can easily manufacture the semiconductordevice which can independently effect writing, erasing and reading onthe two, i.e., first and second floating gate electrodes with onecontrol gate electrode.

[0035] According to a method of manufacturing a semiconductor device ofanother aspect of the invention, a first gate insulating film is formed,and a floating gate electrode is formed on the first gate insulatingfilm. A first interlayer insulating film is formed on an upper surfaceand a side surface of the first floating gate electrode. A second gateinsulating film is formed on a main surface of a semiconductorsubstrate. A second floating gate electrode is formed on the firstinterlayer insulating film and the second gate insulating film to have aportion located above the first floating gate electrode and at least anend extended to a position on the semiconductor substrate near one endof the first floating gate electrode. A second interlayer insulatingfilm is formed at least on an upper surface of the second floating gateelectrode. A control gate electrode is formed on upper surfaces of thefirst and second floating gate electrodes with the first and secondinterlayer insulating films therebetween, respectively. Impurity isintroduced into the semiconductor substrate using the control gateelectrode as a mask to form a first impurity region of a secondconductivity type having a region overlapping with the other end of thefirst floating gate electrode and a second impurity region of the secondconductivity type having a region overlapping with an end of the secondfloating gate electrode.

[0036] According to the method of manufacturing the semiconductor deviceof the above aspect, the first impurity region having the regionoverlapping with the other end of the first floating gate electrode andthe second impurity region having the region overlapping with the oneend of the second floating gate electrode are formed at the same step.Therefore, a manufacturing process can be simplified as compared withthe case where the first and second impurity regions are formed atdifferent steps.

[0037] According to a method of manufacturing a semiconductor device ofstill another aspect of the invention, a gate insulating film is formedon a main surface of a semiconductor substrate. A floating gateelectrode layer is formed on the gate insulating film and issubsequently patterned to form first and second floating gate electrodeson the gate insulating film with a predetermined space between eachother. An interlayer insulating film is formed on upper surfaces andside surfaces of the first and second floating gate electrodes. A secondgate insulating film is formed on a surface of the semiconductorsubstrate located between the first and second floating gate electrodes.A control gate electrode is formed on surfaces of the interlayerinsulating film and the second gate insulating film. Impurity isintroduced into the semiconductor substrate using an end of the firstfloating gate electrode as a mask to form a first impurity region of asecond conductivity type having a region overlapping with the one end ofthe first floating gate electrode. Impurity is introduced into thesemiconductor substrate using an end of the second floating gateelectrode as a mask to form a second impurity region of the secondconductivity type having a region overlapping with the one end of thesecond floating gate electrode.

[0038] Thereby, the manufacturing process can be simplified as comparedwith the case where the first and second impurity regions are formedindependently.

[0039] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0040]FIG. 1 is a cross section of a flash memory of a first embodimentof the invention;

[0041]FIG. 2 shows a concept of variation of characteristics of a memorytransistor caused by writing/erasing of the flash memory of the firstembodiment of the invention;

[0042]FIG. 3 shows a concept of erasing of the flash memory of the firstembodiment shown in FIG. 1;

[0043]FIG. 4 shows a concept of writing of the flash memory of the firstembodiment shown in FIG. 1;

[0044]FIG. 5 shows a concept of reading of the flash memory in an erasedstate shown in FIG. 1;

[0045]FIG. 6 shows a concept of reading of the flash memory in writtenstate shown in FIG. 1;

[0046] FIGS. 7 to 13 are cross sections taken along line perpendicularto the section of the flash memory of the first embodiment shown in FIG.1 and showing 1st to 7th steps in a manufacturing process, respectively;

[0047] FIGS. 14 to 20 are cross sections taken along line parallel tothe section of the flash memory of the first embodiment shown in FIG. 1and showing 1st to 7th steps in a manufacturing process, respectively;

[0048]FIG. 21 is a cross section showing a flash memory of a secondembodiment of the invention;

[0049]FIG. 22 is a cross section showing a flash memory of a thirdembodiment of the invention;

[0050]FIG. 23 is a cross section showing a flash memory of a fourthembodiment of the invention;

[0051]FIG. 24 is a cross section showing a flash memory of a fifthembodiment of the invention;

[0052]FIG. 25 is an equivalent circuit diagram showing a memory cellarray structure of a conventional flash memory;

[0053]FIG. 26 is a plan showing the memory cell array structure of theconventional flash memory;

[0054] FIGS. 27 to 32 are cross sections of a conventional memory cellarray structure taken along line 100-100 in FIG. 26 and showing 1st to6th steps in a manufacturing process, respectively;

[0055] FIGS. 33 to 37 are cross sections of the conventional memory cellarray structure taken along line 200-200 in FIG. 26 and showing 1st to5th steps in the manufacturing process, respectively;

[0056]FIG. 38 shows a concept of variation of characteristics of amemory transistor caused by writing/erasing of the conventional flashmemory;

[0057]FIG. 39 shows a concept of writing of the conventional flashmemory;

[0058]FIG. 40 shows a concept of erasing of the conventional flashmemory;

[0059]FIG. 41 is a flow chart showing writing of the conventional flashmemory; and

[0060]FIG. 42 is a flow chart showing erasing of the conventional flashmemory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] Embodiments of the invention will be described below withreference to the drawings. In a first embodiment, as shown in FIG. 1, afirst impurity diffusion layer 13 and a second impurity diffusion layer14 are formed on a main surface of a semiconductor substrate 101 and arespaced by a predetermined distance to define a channel region 50therebetween. A first floating gate electrode 3 having an endoverlapping with first impurity diffusion layer 13 is formed on channelregion 50 with a first gate insulating film 2 therebetween. A controlgate electrode 5 is formed on first floating gate electrode 3 with afirst interlayer insulating film 4 therebetween. A second interlayerinsulating film 11 is formed on upper and side surfaces of control gateelectrode 5 and side surfaces of first floating gate electrode 3.

[0062] A second gate insulating film 10 continuous to first gateinsulating film 2 is formed on the main surface of semiconductorsubstrate 101. Surfaces of second interlayer insulating film 11 andsecond gate insulating film 10 are covered with a second floating gateelectrode 12. An end of second floating-gate electrode 12 near secondimpurity region 14 overlaps with second impurity diffusion layer 14.Owing to provision of second floating gate electrode as described above,the first embodiment can independently effect writing, erasing andreading on first floating gate electrode 3 and second floating gateelectrode 12 with one control gate electrode 5. Thereby, a memorycapacitance can be doubled while maintaining a memory size similar tothat in the prior art. Consequently, the degree of integration can beimproved substantially double.

[0063] Referring to FIGS. 2 to 6, operation of the flash memory of thefirst embodiment will be described below. In the present invention, thewritten/erased states are opposite to those of the conventional flashmemory already described as the prior art. More specifically, as shownin FIG. 2, the erased state is attained when electrons are held in thefloating gate electrode and the threshold voltage of the memorytransistor viewed from the control gate electrode is high. The writtenstate is attained when electrons are removed from the floating gateelectrode and the threshold voltage of the memory transistor is low.

[0064] Referring first to FIG. 3, the erasing will be described below.For erasing, a voltage Vg of about 10V is applied, for example, tocontrol gate electrode 5, and a voltage Vb of about −10V is applied tothe semiconductor substrate 101 or a well (not shown) formed at thememory transistor. The first and second impurity regions 13 and 14 aresupplied with the same voltage Vb as semiconductor substrate 101 or setto the grounded or open state.

[0065] In the above state, first floating gate electrode 3 has apotential which substantially depends on a capacitance coupling of acapacitance between the control gate electrode and first floating gateelectrode and a capacitance between the first floating gate electrodeand semiconductor substrate, and on a quantity of electrons in the firstfloating gate electrode. A high electric field across the first floatinggate electrode and semiconductor substrate acts to inject electrons intofirst floating gate electrode 3.

[0066] Likewise, second floating gate electrode 12 has a potential whichsubstantially depends on a capacitance coupling of a capacitance betweenthe control gate electrode and second floating gate electrode and acapacitance between the second floating gate electrode and semiconductorsubstrate, and on a quantity of electrons in the second floating gateelectrode. A high electric field across the second floating gateelectrode and semiconductor substrate acts to inject electrons intosecond floating gate electrode 12.

[0067] Referring to FIG. 4, writing will now be described below. Forwriting information into second floating gate electrode 12, i.e., forremoving electrons from second 3 floating gate electrode 12, a negativepotential of about −10V is applied, for example, to control gateelectrode 5, and voltage Vd from about 5V to about 10V is applied tosecond impurity diffusion layer 14. Semiconductor substrate 101 isgrounded, and first impurity diffusion layer 13 is set to the openstate.

[0068] In the above state, second floating gate electrode has apotential which substantially depends on a capacitance coupling of acapacitance between the control gate electrode and second floating gateelectrode and a capacitance between the second floating gate electrodeand second impurity diffusion layer, and on a quantity of electrons inthe second floating gate electrode. A high electric field across thesecond floating gate electrode and second impurity diffusion layer actsto remove electrons in second floating gate electrode 12 toward secondimpurity diffusion layer 14. In this writing, the capacitance betweenthe second floating gate electrode and second impurity diffusion layeris smaller than a capacitance between the second floating gate electrodeand semiconductor substrate, and this difference is larger than thatduring the erasing. Therefore, the potential difference applied forwriting information into the memory transistor can be smaller than thatrequired for the erasing.

[0069] The writing can be effected on first floating gate electrode 3 byapplying similar voltages to control gate electrode 5 and first impuritydiffusion layer 13.

[0070] Based on the principle of writing/erasing, writing can beperformed a bit at a time, and erasing can be performed a control gateat a time. Thereby, the writing/erasing block sizes can be set based onthese units, i.e., bit and control gate.

[0071] Referring to FIGS. 5 and 6, reading will be described below. Whenit is to be read, for example, whether first floating gate electrode 3is in the erased state shown in FIG. 5 or the written state shown inFIG. 6, voltage Vd of from about 1 to about 5V is applied, e.g., tosecond impurity diffusion layer 14, and voltage Vg of about 5V isapplied to control gate electrode 5. When first floating gate electrode3 has accumulated electrons as shown in FIG. 5, i.e., is in the erasedstate, channel region 50 under first floating gate electrode 3 is notinverted by the potential of electrons accumulated in first floatinggate electrode 3, so that a current does not flow through the memorytransistor.

[0072] Meanwhile, when first floating gate electrode 3 has notaccumulated electrons as shown in FIG. 6 i.e., is in the written state,the voltage applied to control gate electrode 5 raises the potential offirst floating gate electrode 3, so that channel region 50 under firstfloating gate electrode 3 is inverted. Second impurity diffusion layer14 and channel region 50 under first floating gate electrode 3 areoffset from each other. In this case, whether a current flows or notdepends on presence and absence of electrons in second floating gateelectrode 12. The condition for voltage application and the quantity ofoffset may be determined to deplete a region under second floating gateelectrode 12 by voltage Vd applied to second impurity diffusion layer14, whereby the current surely flows when electrons are not accumulatedin first floating gate electrode 3, regardless of presence and absenceof electrons in second floating gate electrode 12.

[0073] When information is to be read from second floating gateelectrode 12, this can be done in the same manner as the operation ofreading information from first floating gate electrode 3 describedabove. In this case, voltage Vd is applied to first impurity diffusionlayer 13, and voltage Vg is applied to control gate electrode 5.

[0074] As described above, the flash memory of the first embodiment canindependently effect writing, erasing and reading on the two, i.e.,first and second floating gate electrodes 3 and 13 with one control gateelectrode 5. Therefore, the degree of integration can be substantiallydoubled as compared with the prior art.

[0075] Referring to FIGS. 7 to 20, a process of manufacturing the flashmemory of the first embodiment will be described below. The processsteps shown in FIGS. 7 to 9 and FIGS. 14 and 15 are the same as those inthe conventional process. Thus, the steps from the start to formation ofcontrol electrodes 5 are the same as those in the prior art.

[0076] Then, as shown in FIG. 16, photolithography is used to form aresist pattern 15 exposing only one side of each first floating gateelectrode 3. Using resist pattern 15 and control electrodes 5 as a mask,impurity is ion-implanted into semiconductor substrate 101 to formimpurity diffusion layers 13 of a conductivity type opposite to that ofsemiconductor subs-rate 101 in a self-aligned manner with respect tofirst floating gate electrodes 3.

[0077] As shown in FIGS. 10 to 17, the thermal oxidation method or CVDmethod is executed to form second gate insulating films 10 and secondinterlayer insulating films 11 at the same step. The CVD method is thenexecuted to from a second floating gate layer (not shown) on second gateinsulating films 10 and second interlayer insulating films 11, andsubsequently, photolithography and dry etching technique are used topattern the second floating gate electrode layer. This completes eachfloating gate electrode 12 which covers first floating gate electrode 3and control gate electrode 5 and extends up to a position onsemiconductor substrate 101.

[0078] Thereafter, photolithography is used to from a resist pattern 16exposing only regions not provided with first impurity diffusion layers13. Using resist pattern 16 and second floating gate electrodes 12 as amask, impurity is ion-implanted into semiconductor substrate 101 to formsecond impurity diffusion layers 14 in a self-aligned manner withrespect to second floating gate electrodes 12. Thereafter, resistpattern 16 is removed.

[0079] As shown in FIGS. 11 to 18, an interlayer insulating film 6 isformed by the CVD method similarly to the conventional manufacturingprocess, and subsequently contact holes 7 are formed at interlayerinsulating film 6 by the photolithography and dry etching technique.

[0080] As shown in FIGS. 12 to 19, a metal interconnection layer (notshown) is formed, e.g., by the sputtering method, and subsequently ispatterned by the photolithography and dry etching technique. Thereby, ametal interconnection layer 8 forming the bit lines and source line iscompleted.

[0081] Finally, as shown in FIGS. 13 to 20, a manufacturing processsimilar to the prior art is executed, and more specifically, a surfaceprotective film 9 is formed to cover portions other than bonding padconnections (not shown) by the CVD method.

[0082] As described above, the flash memory of the first embodimentshown in FIG. 1 can be manufactured easily by the manufacturing processsimilar to the prior art.

[0083] Referring to FIG. 21, a flash memory of a second embodiment isdifferent from the first embodiment shown in FIG. 1 in that an end of asecond floating gate electrode 12 a is not extended above impuritydiffusion layer 13 but is located above a region at which control gateelectrode 5 is formed. The other end of second floating gate electrode12 a is formed similarly to the first embodiment, and more specificallyis located over second impurity diffusion layer 14 with second gateinsulating film 10 therebetween.

[0084] Similarly to the first embodiment, the structure described abovecan independently effect writing, erasing and reading on two, i.e.,first and second floating gate electrodes 3 and 12 a with one controlgate electrode 5. As a result, the degree of integration can besubstantially doubled as compared with the prior art. This secondembodiment makes the manufacturing process somewhat difficult ascompared with the first embodiment, because the capacitance between thesecond floating gate electrode and control gate electrode and thecapacitance between the second floating gate electrode and semiconductorsubstrate vary due to mask misregistration between the control gateelectrode and second floating gate electrode.

[0085] In this second embodiment, however, impurity is implanted intosemiconductor substrate 101 with a mask formed of second floating gateelectrode 12 a, control gate electrode 5 and floating gate electrode 3after formation of second floating gate electrode 12 a, so that firstimpurity diffusion layer 13 and second impurity diffusion layer 14 canbe formed at the same step. Therefore, the manufacturing process can befurther simplified as compared with the first embodiment.

[0086] Referring to FIG. 22, a third embodiment is different from thefirst and second embodiments in that a second floating gate electrode 12b is formed under a control gate electrode 5 b. More specifically,second floating gate electrode 12 b is formed on the upper and sidesurfaces of first floating gate electrode 3 with a first interlayerinsulating film 4 b therebetween. An end of second floating gateelectrode 12 b is formed on a region at which first floating gateelectrode 3 is formed, and the other end thereof is extended oversemiconductor substrate 101 to overlap with second impurity diffusionlayer 14 with second gate insulating film 10 therebetween.

[0087] Control gate 5 b is formed on the upper surface of first floatinggate electrode 3 with a first interlayer insulating film 4 btherebetween, and is formed also on side and upper surfaces of secondfloating gate electrode 12 b with a second interlayer insulating film 11b therebetween. A side surface of control gate electrode 5 b and a sidesurface of first floating gate electrode 3 adjacent thereto are alignedsubstantially on the same straight line, and the other side surface ofcontrol gate electrode 5 b and a side surface of second floating gateelectrode 10 b adjacent thereto are aligned substantially on the samestraight line.

[0088] The flash memory of the third embodiment described above ismanufactured by the following process. The process steps from the startto formation of first floating gate electrode 3 are the same as those inthe prior art. Thereafter, a second interlayer insulating layer (notshown) and a second floating gate electrode layer (not shown) on thesame are formed and subsequently patterned by the photolithography anddry etching technique to form second interlayer insulating film 4 b andsecond floating gate electrode 12 b.

[0089] Then, a second interlayer insulating layer (not shown) and acontrol gate electrode layer (not shown) are formed and subsequentlypatterned by the photolithography and dry etching technique to formsecond interlayer insulating film 11 b and control gate electrode 5 b.Simultaneously with the patterning for forming control gate electrode 5b, the patterning may be effect on the end of first floating gateelectrode 3 and the end of second floating gate electrode 12 b remotefrom overlapped portions of first and second floating gate electrodes 3and 12. Thereby, one side surface of gate electrode 5 b and one sidesurface of first floating gate electrode 3 are formed substantially onthe same straight line, and the other side surface of control gateelectrode 5 b and one side surface of second floating gate electrode 12b are formed substantially on the same straight line. In this case,control gate electrode 5 b is formed and subsequently impurity isimplanted into semiconductor substrate 101 using control gate electrode5 b as a mask, so that first and second impurity diffusion layers 13 and14 are formed in a self-aligned manner with respect to control gateelectrode 5 b (i.e., first and second floating gate electrodes 3 and 5b). Therefore, this embodiment can further simplify the manufacturingprocess as compared with the first embodiment.

[0090] Thereafter, steps similar to those in the prior art are executedto form interlayer insulating film 6, contact holes 7, metalinterconnection layer 8 and surface protective film 9. This thirdembodiment can employ the method similar that of the first embodiment sothat writing, erasing and reading can be effected on first and secondfloating gate electrodes 3 and 5 b with one control gate electrode 5 b.Thereby, the third embodiment can substantially double the degree ofintegration similarly to the first and second embodiments.

[0091] Referring to FIG. 23, a fourth embodiment is provided with afirst floating gate electrode 3 c and a second floating gate electrode12 c which are spaced by a predetermined distance and are formed on themain surface of semiconductor substrate 101 with a first gate insulatingfilm 2 c therebetween. A control gate electrode 5 c is formed on aregion of semiconductor substrate 101 between first and second floatinggate electrodes 3 c and 12 c with a second gate insulating film 15 ctherebetween, and is formed also on upper and side surfaces of first andsecond floating gate electrodes 3 c and 12 c with a first interlayerinsulating film 4 c therebetween. The memory transistor size in thefourth embodiment thus constructed is somewhat larger than that in thefirst to third embodiments.

[0092] In this fourth embodiment, however, first and second floatinggate electrodes 3 c and 12 c can be formed at the same step, so that themanufacturing process can be simpler than those in the first to thirdembodiments. Also in this fourth embodiment, control gate electrode 5 ccovers the side surfaces of first and second floating gate electrodes 3c and 12 c with first interlayer insulating film 4 c therebetween, sothat a capacitance between first and second floating gate electrodes 3 cand 12 c and control gate electrode 5 c is larger than those in thefirst to third embodiments. This increases a capacitance coupling ratio,so that the potential of first floating gate electrode 3 c duringwriting and erasing is larger than those in the first to thirdembodiments. This advantageously facilitates the writing and erasing.

[0093] In the fourth embodiment, first and second floating gateelectrodes 3 c and 12 c must be spaced by a distance larger than theresolution limit in the photolithographic step, resulting in reductionof the degree of integration. However, there is such an advantage overthe prior art that memory elements at a high density can be manufacturedby the process steps substantially equal in number to those in the priorart.

[0094] In this fourth embodiment, a parasitic transistor, in which agate insulating film is formed of second gate insulating film 10 c and agate electrode is formed of control gate electrode 5 c, is formedbetween first floating gate electrode 3 c and second floating gateelectrode 12 c. However, this parasitic transistor has a thresholdvoltage lower than that of the memory cell transistor. Therefore,whenever the memory transistor is turned on, the parasitic transistor isturned on, so that no disadvantage is caused. The writing, erasing andreading similar to those in the first to third embodiments can beexecuted in this fourth embodiment.

[0095] In the manufacturing process of the flash memory of the fourthembodiment, a first gate insulating layer (not shown) is formed on themain surface of semiconductor substrate 101, and a floating gateelectrode layer (not shown) is formed on the first gate insulatinglayer. Then, the floating gate electrode layer and first gate insulatinglayer are patterned by the photolithography and dry etching technique toform first and second floating gate electrodes 3 c and 12 c on firstgate insulating film 2 c with a predetermined space between each other.Thereafter, an insulating layer (not shown) is formed on the wholesurface and a control gate electrode layer (not shown) is formed on thesame. These layers are patterned by the photolithography and dry etchingtechnique to form second gate insulating film 10 c, first interlayerinsulating film 4 c and control gate electrode 5 c.

[0096] Simultaneously with the patterning of control gate electrode 5 c,the patterning may be effected on ends of first and second floating gateelectrodes 3 c and 12 c near first and second impurity diffusion layers13 and 14. In this case, after patterning control gate electrode 5,impurity is ion-implanted into semiconductor substrate 101 usingpatterned control gate electrode 5 as a mask. Thereby, first and secondimpurity diffusion layers 13 and 14 can be formed in a self-alignedmanner with respect to first and second floating gate electrodes 3 c and12 c, respectively. Thereafter, process steps similar to those in theprior art are executed to form interlayer insulating film 6, contactholes 7 metal interconnection layer 8 and surface protective film 9.

[0097] Referring to FIG. 24, a fifth embodiment includes a thirdimpurity diffusion later 30 formed on a surface of a region ofsemiconductor substrate 101 at which a parasitic transistor is formed inthe structure of fourth embodiment. Provision of third impuritydiffusion layer described above can advantageously prevent formation ofa parasitic transistor. For forming the structure including thirdimpurity diffusion layer 30, first and second floating gate electrodes 3c and 12 c are patterned, and subsequently ion is implanted intosemiconductor substrate 101 using first and second floating gateelectrodes 3 c and 12 c as a mask. Thereby, first, second and thirdimpurity diffusion layers 13, 14 and 30 are formed.

[0098] As described above, the semiconductor device of an aspect of theinvention can independently effect writing, erasing and reading on thetwo, i.e., first and second floating gate electrodes with one controlgate electrode. Therefore, the degree of integration can be improvedremarkably as compared with the prior art.

[0099] According to the method of manufacturing the semiconductor deviceof another aspect of the invention, the first impurity region having aregion overlapping with an end of the first floating gate electrode isformed using the first floating gate electrode as a mask, and the secondimpurity region having a region overlapping with an end of the secondfloating gate electrode is formed using the second floating gateelectrode as a mask, thereby it is possible to manufacture easily thesemiconductor device which can independently effect writing, erasing andreading on the two, i.e., first and second floating gate electrodes withone control gate electrode.

[0100] According to the method of manufacturing the semiconductor deviceof still another aspect of the invention, impurity is introduced intothe semiconductor substrate using the control gate electrode as a mask,so that the first impurity region having a region overlapping with theother end of the first floating gate electrode and the second impurityregion having a region overlapping with an end of the second floatinggate electrode are formed, whereby it is possible to simplify theprocess of manufacturing the semiconductor device, which canindependently effect writing, erasing and reading on the two, i.e.,first and second floating gate electrodes with one control gateelectrode.

[0101] According to the method of manufacturing the semiconductor deviceof yet another aspect of the invention, the floating gate electrodelayer is formed on the first gate insulating film, and then is patternedto form the first and second floating gate electrodes on the first gateinsulating film with a predetermined space between each other, so thatthe manufacturing process can be simpler than that in the case where thefirst and second floating gate electrodes are independently formed.

[0102] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate of a first conductivity type having a mainsurface; first and second impurity regions of a second conductivity typeformed on the main surface of said semiconductor substrate with apredetermined space defining a channel region between each other; afirst floating gate electrode formed on said channel region with a firstgate insulating film therebetween and having an end overlapping withsaid first impurity region; a control gate electrode formed on an uppersurface of said first floating gate electrode with a first interlayerinsulating film therebetween; and a second floating gate electrodeformed on an upper surface and a side surface of said control gateelectrode with a second interlayer insulating film therebetween andformed on said channel region with a second gate insulating filmtherebetween to have an end overlapping with said second impurityregion.
 2. The semiconductor device according to claim 1, wherein saidsecond floating gate electrode has a portion extending over said firstimpurity region with said second gate insulating film therebetween. 3.The semiconductor device according to claim 1, wherein said secondfloating gate electrode has the other end located above a region forforming said control gate electrode.
 4. The semiconductor deviceaccording to claim 1, wherein a side surface of said first floating gateelectrode and a side surface of said control gate electrode aresubstantially linearly aligned to each other.
 5. A semiconductor deviceallowing electrical writing and erasing of information comprising: asemiconductor substrate of a first conductivity type having a mainsurface; first and second impurity regions of a second conductivity typeformed on the main surface of said semiconductor substrate with apredetermined space defining a channel region between each other; afirst floating gate electrode formed on said channel region with a firstgate insulating film therebetween and having an end overlapping withsaid first impurity region; a second floating gate electrode formed onan upper surface and a side surface of said first floating gateelectrode with a first interlayer insulating film therebetween andformed on said channel region with a second gate insulating filmtherebetween to have an end overlapping with said second impurityregion; and a control gate electrode formed on the upper surface of saidfirst floating gate electrode with said first interlayer insulating filmtherebetween and formed on a side surface and an upper surface of saidsecond floating gate electrode with a second interlayer insulating filmtherebetween.
 6. The semiconductor device according to claim 5, whereinsaid second floating gate electrode has the other end located above aregion for forming said first floating gate electrode, an end of saidcontrol gate electrode has a side surface substantially linearly alignedto a side surface of an end of said first floating gate electrode, andthe other end of said control gate electrode has a side surfacesubstantially linearly aligned to a side surface of the other end ofsaid second floating gate electrode.
 7. A semiconductor device allowingelectrical writing and erasing of information comprising: asemiconductor substrate of a first conductivity type having a mainsurface; first and second impurity regions of a second conductivity typeformed on the main surface of said semiconductor substrate with apredetermined space defining a channel region between each other; afirst floating gate electrode formed on said channel region with a firstgate insulating film therebetween and having an end overlapping withsaid first impurity region; a second floating gate electrode formed onsaid channel region with a first gate insulating film therebetween toform a predetermined space with respect to said first floating gateelectrode and having an end overlapping with said second impurityregion; and a control gate electrode formed on upper surfaces and sidesurfaces of said first and second floating gate electrodes with a firstinterlayer insulating film therebetween and formed on said channelregion with a second gate insulating film therebetween.
 8. Asemiconductor device according to claim 7, wherein said channel regionis provided at its region located between said first floating gateelectrode and said second floating gate electrode with a third impurityregion.
 9. The semiconductor device according to claim 7, wherein an endof said control gate electrode has a side surface substantially linearlyaligned to a side surface of an end of said first floating gateelectrode, and the other end of said control gate electrode has a sidesurface substantially linearly aligned to a side surface of the otherend of said second floating gate electrode.
 10. A method ofmanufacturing a semiconductor device comprising the steps of: forming afirst gate insulating film on a main surface of a semiconductorsubstrate of a first conductivity type; forming a first floating gateelectrode on said first gate insulating film; forming a control gateelectrode on said first floating gate electrode with a first interlayerinsulating film therebetween; introducing impurity into saidsemiconductor substrate using said first floating gate electrode as amask to form a first impurity region of a second conductivity typehaving a region overlapping with an end of said first floating gateelectrode; forming a second interlayer insulating film on an uppersurface and a side surface of said control gate electrode and a sidesurface of said first floating gate electrode; forming a second gateinsulating film on the main surface of said semiconductor substrate;forming a second floating gate electrode on said second interlayerinsulating film and said second gate insulating film to have a portionlocated on said control gate electrode and at least an end extended to aposition on said semiconductor substrate near the other end of saidfirst floating gate electrode; and introducing impurity into saidsemiconductor substrate using said second floating gate electrode as amask to form a second impurity region of the second conductivity typehaving a region overlapping with an end of said second floating gateelectrode.
 11. The method of manufacturing the semiconductor deviceaccording to claim 10, wherein said first and second impurity regionsare formed at the same step after formation of said second floating gateelectrode.
 12. The method of manufacturing the semiconductor deviceaccording to claim 10, wherein said second interlayer insulating filmand said second gate insulating film are formed at the same step.
 13. Amethod of manufacturing a semiconductor device comprising the steps of:forming a first gate insulating film on a main surface of asemiconductor substrate of a first conductivity type; forming a firstfloating gate electrode on said first gate insulating film; forming afirst interlayer insulating film on an upper surface and a side surfaceof said first floating gate electrode; forming a second gate insulatingfilm on the main surface of said semiconductor substrate; forming asecond floating gate electrode on said first interlayer insulating filmand said second gate insulating film to have a portion located abovesaid first floating gate electrode and at least an end extended to aposition on said semiconductor substrate near one end of said firstfloating gate electrode; forming a second interlayer insulating film atleast on an upper surface of said second floating gate electrode;forming a control gate electrode on upper surfaces of said first andsecond floating gate electrodes with said first and second interlayerinsulating films therebetween, respectively; and introducing impurityinto said semiconductor substrate using said control gate electrode as amask to form a first impurity region of a second conductivity typehaving a region overlapping with the other end of said first floatinggate electrode and a second impurity region of the second conductivitytype having a region overlapping with an end of said second floatinggate electrode.
 14. The method of manufacturing the semiconductor deviceaccording to claim 13, wherein said first interlayer insulating film andsaid second gate insulating film are formed at the same step.
 15. Amethod of manufacturing a semiconductor device comprising the steps of:forming a gate insulating film on a main surface of a semiconductorsubstrate of a first conductivity type; forming first and secondfloating gate electrodes on said gate insulating film with apredetermined space between each other by forming a floating gateelectrode layer on said gate insulating film and subsequently patterningsaid floating gate electrode layer; forming an interlayer insulatingfilm on upper surfaces and side surfaces of said first and secondfloating gate electrodes; forming a second gate insulating film on asurface of said semiconductor substrate located between said first andsecond floating gate electrodes; forming a control gate electrode onsurfaces of said interlayer insulating film and said second gateinsulating film; introducing impurity into said semiconductor substratewith an end of said first floating gate electrode as a mask to form afirst impurity region of a second conductivity type having a regionoverlapping with said one end of said first floating gate electrode; andintroducing impurity into said semiconductor substrate using an end ofsaid second floating gate electrode as a mask to form a second impurityregion of the second conductivity type having a region overlapping withsaid one end of said second floating gate electrode.
 16. The method ofmanufacturing the semiconductor device according to claim 15, whereinsaid interlayer insulating film and said second gate insulating film areformed at the same step.